1. Field of the Invention
This invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device having two different active elements of bipolar-CMOS structure whose drain and base are used as a common area, and to a method for manufacturing the same.
2. Description of the Related Art
Using conventional semiconductor technology, various types of semiconductor devices of bipolar-CMOS (which is hereinafter referred to as Bi-CMOS) structure--which structure permits a bipolar circuit and a CMOS circuit to be formed on the same chip--have been developed. An example of a semiconductor device of Bi-CMOS structure is disclosed in U.S. Pat. No. 4,616,146. FIG. 1 shows a typical example of the prior art circuit construction of a semiconductor device of this structure.
Referring to FIG. 1, drain D of P-channel MOSFET Q1 is connected to the base of NPN bipolar transistor Q2. The drain current of MOSFET Q1 is amplified by NPN bipolar transistor Q2, with the result that, the circuit constructed thus is able to supply a large current. Transistors Q1' and Q2' are of the same type as transistors Q1 and Q2.
A cross sectional view of an element of a transistor forming area, which is a part of a Bi-CMOS composite circuit, is shown in the article "2 MICRON MERGED BIPOLAR-CMOS TECHNOLOGY" by A. R. Alvarez, P. Meller and B Tien of Motorola Inc., Mesa in IEDM 84 pp. 761-764.
Hitherto, in a semiconductor device of the type shown in FIG. 1, for example, an N.sup.+ -type buried collector diffusion layer, P-type epitaxial layer, N.sup.- -type collector diffusion layer and N.sup.+ -type electrode lead-out area are formed on a P-type semiconductor substrate by use of the well known ion-implantation technique, epitaxial growth, thermal diffusion technique and the like. P-channel MOSFET Q1 and NPN bipolar transistor Q2 are respectively formed in different areas of the N.sup.- -type collector layer. Drain D of P-channel MOSFET Q1 and base B of bipolar transistor Q2 are connected to each other by means of a wiring member such as an aluminum layer formed outside the element area. In this way, a semiconductor device having multi-functions can be obtained by simultaneously effecting the processes of manufacturing MOSFET Q1 and bipolar transistor Q2.
However, in the semiconductor device with the above-described structure, wiring regions for making electrical connection with the two different active elements are formed in different positions and therefore the chip area cannot be reduced.